1. Field of the Invention
This invention relates to circuitry that utilizes field effect transistors (FET) and more particularly to circuitry that provides protection from voltage levels above an acceptable CMOS operating voltage range and from other forms of device degradation.
2. Description of the Background
Continuing development of semi-conductor devices for use in input/output (I/O) circuitry has resulted in semi-conductor devices that have smaller oxide thickness. The smaller oxide thicknesses, has in turn translated into a reduction in voltage ratings of the semi-conductor devices. At times, such semi-conductor devices must be able to communicate with a higher voltage rail legacy interface. Legacy interfaces have voltage rails typically greater than 2.5V. Vmax is the highest voltage rating of a semi-conductor device that if exceeded, will result in the destruction of the device during operation. FIG. 1 shows a prior art example of an FET semi-conductor device in which a voltage rail in excess of the device's Vmax would cause its destruction. Currently known solutions to this problem rely on large resistor networks to reduce circuit voltage levels. However, such an arrangement draws large amounts of power.
What is needed is a more effective technique for protecting semi-conductor devices employed in connection with the higher voltage rails of certain legacy circuits.